The present invention relates to semiconductor devices, and more specifically, fin-like field effect transistors (FinFET).
Field effect transistors (FETs) include a source, a gate, and a drain. The action of the FET depends on the flow of majority carriers along a channel between the source and drain that runs past the gate. Current through the channel, which is between the source and drain is controlled by the transverse electric field under the gate. The length of the gate determines how fast the FET switches, and can be about the same length as the channel.
The size of FETs has been successfully reduced through the use of one or more fin-shaped channels. A FET employing such a channel structure can be referred to as a FinFET. Previously, complementary metal-oxide semiconductor (CMOS) devices were substantially planar along the surface of the semiconductor substrate, the exception being the FET gate that was disposed over the top of the channel. Fins break from this paradigm by using a vertical channel structure in order to maximize the surface area of the channel that is exposed to the gate. The gate controls the channel more strongly because it extends over more than one side (surface) of the channel.
A challenge in fabricating multi-gate FETs is the inherently high parasitic capacitance as compared to conventional planar FETs. A need exists for a finFET with reduced parasitic capacitance.